Split gate non-volatile flash memory cells having a select gate, a floating gate, a control gate and an erase gate are well known in the art. See for example U.S. Pat. Nos. 6,747,310 and 7,868,375. It is also known to form logic devices (i.e., low voltage and/or high voltage logic devices) on the same silicon chip, and in doing so sharing some of the processing steps for forming portions of both the memory and logic devices (e.g. forming gates for both memory cells and logic devices using the same polysilicon deposition process). However, other processing steps in forming the memory cells can adversely affect the previously fabricated logic devices, and vice versa, so it often can be difficult and complex to form both types of devices on the same wafer.
To solve problems with reduced channel widths by shrinking lithography size, Fin-FET types of structures have been proposed for memory cell structures. In a Fin-FET type of structure, a fin shaped member of semiconductor material connects the source to the drain regions. The fin shaped member has a top surface and two side surfaces. Current from the source to the drain regions can then flow along the top surface as well as the two side surfaces of the fin shaped member. Thus, the effective width of the channel region is increased, thereby increasing the current flow. However, the effective width of the channel region is increased without sacrificing more semiconductor real estate by “folding” the channel region into two side surfaces, thereby reducing the “footprint” of the channel region. Non-volatile memory cells using such Fin-FETs have been disclosed. Some examples of prior art Fin-FET non-volatile memory structures include U.S. Pat. Nos. 7,423,310, 7,410,913 and 8,461,640. What these prior art references do not contemplate is a Fin-FET type configuration for logic devices formed on the same wafer substrate as non-volatile memory cells of a non-Fin-FET type configuration.